A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric

An analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated.