Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies

A review of the channel hot carrier (CHC) mechanism and its effects on n-MOSFET devices of deep submicron CMOS bulk technologies is presented. Even with power supply reduction (Vsupply ≈ 1.0 V) CHC effects still limit aggressive transistor scaling. In this work it is shown that the “Lucky Electron Model” picture is not adequate to describe carrier heating under quasi ballistic transport. A more general physical picture is proposed, in which the driving force of the hot carrier damage is the “carrier dominant energy” determined by the energy convolution of the effective interface states generation (ISG) cross section (SIT(E)) and the electron energy distribution function (EEDF) at given bias stress conditions. Both the CHC LEM and the energy driven approximations are derived. The latter is shown to be more adequate to describe the CHC degradation with supply voltage reduction. This approach allows an experimental quantification of SIT(E).