Effect of process-induced voids on isothermal fatigue resistance of CSP lead-free solder joints

With the progressive miniaturization of electronic devices, process-induced voids in lead-free solder joints affect the assessment of thermal fatigue resistance. Voids appear randomly in a solder joint, making quantitative evaluation of fatigue life difficult. This study examined the effect of process-induced voids on the thermal fatigue resistance of CSP solder joints. CSP specimens were subjected to isothermal mechanical fatigue tests; specifically, the accelerated thermal cycle test. When a void is small, it has no apparent effect on fatigue life. However, when voids having diameters of at least 30% of solder diameter are located along the crack propagation route, fatigue life is shortened. FEA and Miner’s law for estimation of fatigue life suggest that voids affect not only the crack initiation but also crack propagation. Estimated numbers of cycles to failure agree quantitatively with the experimental results. The effects of the size, location, and number of voids can be extracted by FEA. As voids along the crack path become larger, fatigue life decreases. Moreover, when two voids are located near the corner of a solder joint on the crack path, a 30% decrease in life appears. This result agrees with experimental results reported in several literatures.