A methodology for the calculation of stress migration in die-level interconnects

An analytic methodology is presented for the examination of stress migration in the built up interconnect structures on integrated circuit die. The methodology uses finite element analysis combined with a presumed diffusion mechanism to define a vacancy accumulation site and to characterize the flux of vacancies. This physics-based approach accounts for the effects of time, temperature, material systems and interconnect geometry on stress migration. The method should be generally applicable to a wide range of interconnect structures and will find utility in the design of stress migration tolerant designs as well as in failure analysis.Through examples, stress migration within copper lines and vias with low-k and SiO2 dielectrics is examined. The methodology predicts increased vacancy fluxes with increases in exposure time, line width and temperatures within the range studied. A fundamental mechanism suggesting heightened vacancy fluxes with a low-k dielectric over a SiO2 dielectric is described. Finally, the methodology is exercised to demonstrate that the apparent activation energy obtained through stress migration testing of built up interconnect structures may not correspond with the governing diffusion mechanism.