کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
546117 | 1450563 | 2006 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
We investigate in this paper board-level drop reliability of chip-scale packages subjected to JEDEC drop test condition B, which features an impact pulse profile with a peak acceleration of 1500G and a pulse duration of 0.5 ms. Effects of Sn–Ag–Cu or Sn–Pb solder joint compositions, fluxes, and substrate pads with Ni/Au surface finish or OSP coating on the drop reliability of the board-level test vehicle are compared. Locations and modes of the failed solder joints are examined using the dye stain test. The results indicate that solder joints with a low Ag weight content and substrate pads with OSP coating both enhance the drop resistance of the board-level test vehicle.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 46, Issues 2–4, February–April 2006, Pages 645–650
Journal: Microelectronics Reliability - Volume 46, Issues 2–4, February–April 2006, Pages 645–650
نویسندگان
Yi-Shao Lai, Ping-Feng Yang, Chang-Lin Yeh,