Determining factors affecting ESD failure voltage using DOE

Factors influencing machine model (MM) ESD failure voltage are investigated in two statistically designed experiments. Several variables (or factors), namely wafer lot, type of ESD handling procedure, pulse polarity order and assembly house are studied. The results are examined using three methods: survival analysis, logistic regression and an empirical approach. Each method can be used to predict the cumulative distribution function (cdf) which is the probability of failure on or before a particular voltage. Survival analysis treats the failure voltage as a response to the settings of the various factors. The failure voltage is analogous to the “failure time”. This method predicts the cdf given the settings of the different variables. In contrast, logistic regression treats voltage as a factor, along with the other variables and will similarly predict the cdf given the settings of all the factors. The empirical approach is used to estimate the cdf using only the distribution of failure voltages for each run in a designed experiment and is not derived from the factor settings. This third approach can be used as a check on the first two.In the first DOE, the factors wafer lot, level of ESD-safe handling, pulse polarity order and their interactions are found to change the predicted median failure voltage from ∼19 to ∼34 V, a swing of ±30% from the overall median ∼26 V. The effect of wafer lot along with the interaction between the level of ESD protection and pulse polarity order are found to be statistically significant. In the second DOE, only the effects of wafer and assembly house are studied. Here, just wafer has a significant effect. The range of ESD failure voltages is much smaller in round 2 (∼30 to ∼36 V).Although the failure voltages reported here are relatively low, the methods described herein are general. Thus, the approaches described can be applied to circuits with much higher ESD failure voltages.