A transient noise simulation model for the analysis of the optimal number of stages of the analog accumulator in TDI CMOS image sensors

• A fast transient noise simulation model is proposed to analyze the optimal stages for the analog accumulator in a fixed silicon area.
• Because the analog accumulator is a linear time-varying system, the transient noise simulation (TNS) is required to prove the analysis of the optimal stage which will take a long time. In order to accelerate our analysis, a fast transient noise simulation model (TNSM) is proposed and proved to be effective by the TNS.

In this paper, a fast transient noise simulation model is proposed to analyze the optimal number of stages for the maximum signal to noise ratio (SNR) of the analog accumulator in a fixed silicon area. The Transient Noise Simulation (TNS) is required to confirm the analysis of the optimal number of stages, which requires long simulation time. In order to accelerate our analysis, a fast transient noise simulation model (TNSM) is proposed based on the noise analysis and shown to be effective by TNS. Numerical analysis is verified by the TNSM, and it indicates that the optimal number of stages in a fixed area changes with the noise of the input signal.