Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

• Vt instability at steady phase is attributed to lateral charges transport model.
• Higher P/E cycle counts increase Vt instability at steady phase.
• Higher bake temperatures enhance Vt instability at steady phase.
• Cycling alters trapped charge profile that dictates Vt instability at steady phase.

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.