A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits

• A holistic compact model for NBTI induced degradation and recovery.
• A block-based timing analysis which can consider variations in the use profile of an integrated circuit.
• Analysis of the impact of high-level design decisions, such as DVS, on aging degradation.

We present an aging analysis which considers variations in chip environment and workload as they are caused by dynamic voltage or frequency scaling, power-down modes, etc. Therefore, we developed a model for NBTI degradation and recovery based on trapping/detrapping. Our model accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology. The aging analysis utilizes this model to consider variations in environment and workload. Results show that our analysis can be used for system-level design decisions and reduces substantially estimated degradation.