Analytical compact modeling and statistical variability study of LDMOS

• An analytical IV compact model is constructed for high-voltage LDMOS with explicit calculation of the internal drain voltage.
• This compact model is verified by comparing to TCAD simulations and measurement data.
• This compact model is utilized to study statistical variability in LDMOS devices.

In this paper, we present an analytical IV model for high-voltage LDMOS. The model is surface potential based, and explicit calculation of the internal drain voltage is achieved by unified regional formulation of the drift resistance. High-voltage effects such as quasi-saturation and impact ionization are well captured. The compact model is verified with TCAD simulations and measurement data in all operating ranges. In addition, this model is utilized to study the statistical variability in LDMOS devices. Under the assumption of uncorrelated normal distribution of device parameters, variations in physical device parameters can be directly related to the variations in performance target variables with the aid of the compact model, which can be useful in device optimization.