Modeling and analysis of gate-all-around silicon nanowire FET

• We model the gate-all-around (GAA) silicon nanowire (SiNW) FET in TCAD.
• We discuss the carrier transport physics in the modeling.
• We investigate the self-heating effect and process induced stress effect.
• Advantages of GAA SiNW FET are evaluated by comparing with FinFET.

In this paper, we report the TCAD study on gate-all-around (GAA) silicon nanowire (SiNW) FET. The device carrier transport physics, self-heating effect and process induced stress effect are discussed. With a comparison study between GAA SiNW FET and FinFET, the advantages of GAA SiNW FET on gate controllability and short channel effect immunity are evaluated.