Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

• An Al/Al2O3/HfLaON/(TaON/SiO2)/Si high-k gate stack structure is proposed.
• A band-engineered dual tunneling layer (TaON/SiO2) is proposed and prepared.
• A good trade-off among the memory characteristics is obtained.
• In-situ sputtering method is employed to fabricate the proposed structure.

Tunneling–barrier engineered stacks with different high-κ dielectrics are investigated by fabricating the stacked structures of Al/Al2O3/HfLaON/ (TaON/SiO2)/Si and Al/Al2O3/HfLaON/ (HfON/SiO2)/Si. As compared to the device with HfON/SiO2 dual tunnel layer (DTL), the one with TaON/SiO2 DTL shows larger memory window (3.85 V at ± 13 V/1 s), higher program/erase speeds (1.85 V/−2.00 V at ± 12 V/100 μs), better endurance (window narrowing rate of 5.7% after 105 cycles). The main mechanisms involved lie in (1) the higher dielectric constant of TaON which induces high electric field in the SiO2 layer, (2) the smaller conduction/valence-band offsets between TaON and the Si substrate, and (3) better interface quality with SiO2. Furthermore, compared with SiO2 single tunnel layer, better retention characteristics can be achieved for the TaON/SiO2 DTL due to its larger thickness.