Measuring seam/crack formation in interconnect metallization

Low cost processes, in both GaAs and Silicon, often use non-planar interconnect metals. While very efficient in simplifying processes, seam (more commonly called “crack”) formation due to inter-level dielectric topologies can (1) cause significant thinning in the metallization, impacting the reliability and (2) act as process defects that reduces circuit yield. To better understand and monitor crack formation, we used a series of test structures to develop an electrical test allowing crack formation to be characterized. We confirmed our results with cross sections. The methodology presented here is also used to characterize new process steps or processes to verify the new process make cracking worse. In the first application of this method, it highlighted a potential cracking issue, preventing it from propagating into production.