Via high resistance failure analysis of LSI devices induced by multiple factors related to process and design

We investigated the root cause of a via high resistance issue due to fabrication process variations and mismatching design rule. Physical analyses of localized chip area including a failed via were first performed using cross-sectional TEM-EDX, EBSP and CL methods. These analyses results revealed the root causes as the formation of a TixAly layer, porous and small void areas around the failed via bottom due to poor step coverage of the TiN/Ti barrier layer and the growth of the voids by tensile residual-stress in Al line. Next, to improve design rule, the dependencies of failure sites on cell structure and layout were evaluated by design analysis of the whole chip area. To realize this analysis, we developed a simple SEM observation method of the TixAly layer using a combination of polishing and RIE techniques. This analysis result indicated the via high resistance issue tends to occur at only VIA1 of high-driver cells that have many fan-outs. From these combined analyses regarding fabrication and design, we found that METAL1 layout and the location of the VIA1 on METAL1 influence TixAly and voids formation. In other words, metal line design rule is related strongly to this via high resistance issue.