Efficiently analyzing the impact of aging effects on large integrated circuits

Time-dependent variations have not received a lot of attention in the past. However, they gain in importance with each now process generation. Our goal is an accurate analysis of the timing degradation of large integrated circuits caused by aging effects. We present an aging-analysis flow on gate level that considers the two dominant aging-effects, NBTI and HCI. Furthermore, an aging model on module-level is proposed to handle even larger circuits. This aging model is on average 30× faster than an analysis on gate level while providing the same accuracy.