Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.