Single event upset mitigation by means of a sequential circuit state freeze

This paper describes a novel design technique for hardening sequential circuits against Single Event Transients (SETs) and Single Event Upsets (SEUs) in non-volatile FPGAs. Double Modular Redundancy (DMR) is used to detect the presence of a SET in a sequential circuit. However, DMR solutions are only able to detect SET’s and not mask or correct them. Therefore, extra functionality is required to mask and correct the error after it has been detected. The central idea of the method proposed is to “freeze” the sequential circuit at a particular state when a SET is detected. As soon as the SET dissipates, the circuit is “unfrozen” so that it can continue with normal operation. Due to the short SET lifetime versus much longer circuit clock periods, the “frozen” state will normally not last more than one clock period. The proposed scheme is suitable for delay-insensitive applications requiring minimal hardware overhead.The proposed DMR method is thoroughly tested on ITC99 benchmarks. With a small delay of one clock period whenever a SET is detected, the proposed method offers immunity against the errors caused by SETs in non-volatile FPGA systems.

► “Freeze” the sequential circuit at a particular state when a SET is detected.
► When the SET dissipates, the circuit is unfrozen to continue with normal operation.
► The “frozen” state will normally not last more than one clock period.
► The proposed scheme is suitable for delay-insensitive applications.
► Immunity against the errors caused by SETs in non-volatile FPGA systems.