Fault model for on-chip communication and joint equalization and special spacing rules for on-chip bus design

Achieving high speed and reliability is a key challenge in on-chip bus design. To address the challenge, in this paper we propose a fault model for on-chip communication and further develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and communication reliability for on-chip buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the buses to achieve high-speed and high-reliability of the buses. Special spacing rules use the sufficient spacing between the adjacent wires to mitigate the crosstalk effect from the adjacent wires. The joint scheme equalization and special spacing rules exploits their respective advantages to further improve the speed and communication reliability of the buses. The simulation results show that the joint scheme equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The bit error rate of the bus can be improved from 10−5 to 10−24.

► A fault model for on-chip communication is established in the paper.
► A joint scheme equalization and special spacing rules for on-chip buses is proposed.
► The joint scheme can reduce 50% delay and save 42% power with 52% area overhead.
► The bit error rate of the bus can be improved from 10−5 to 10−24.