A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell

This paper presents a technique for designing a variability aware SRAM cell. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that the access pass gates are replaced with full transmission gates. The paper studies the impact of Vt (threshold voltage) variation on most of the design metrics of SRAM cell. The proposed design achieves 1.4× narrower spread in IREAD at the expense 1.2× lower IREAD at nominal VDD. It offers 1.3× improvements in TRA (read access time) distribution at the expense of 1.2× penalty in read delay. The proposed bitcell offers 1.1× tighter spread in TWA (write access time) incurring 1.3× longer write delay. It shows 180 mV of SNM (static noise margin) and is equally stable in hold mode. It offers 1.3× higher RSNM (100 mV) compared to 6T (75 mV). It exhibits improved SINM (static current noise margin) distribution at the expense of 1.6× lower WTI (write trip current). It offers 1.05× narrower spread in standby power. Thus, comparative analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of Vt variation to a large extent.

► A technique for designing a variability aware SRAM cell in 16 nm technology node is presented.
► Impact of process, voltage, and temperature variations on design metrics are investigated.
► Significant improvements in variability are achieved proving robustness of proposed design.