Oxide reliability below 3 nm for advanced CMOS: Issues, characterization, and solutions

This tutorial is devoted to oxide reliability below 3 nm in advanced CMOS devices. Indeed, with device dimension downscaling, the oxide thickness reduction below 6 nm has led to important changes in degradation mechanisms and failure modes and this trend has been enhanced below 3 nm. The topics addressed will cover basic aspects, from ITRS predictions to a clear definition of various oxide breakdown events and failure modes and will detail the changes linked to thickness reduction below 3 nm, essentially due to the increasing importance of direct tunneling current through the oxide. Experimental aspects will be highlighted and the statistical treatment using Weibull statistics will be detailed. On the basis of well established experimental points, we will review models for temperature, oxide thickness and voltage dependence of time to breakdown, and will point out the influence of some process factors. In conclusion, we will give some elements concerning the usability of devices and circuits after breakdown.