Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N−channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO2/Si barrier.