Analysis of hot carrier effects in a 0.35 μm high voltage n-channel LDMOS transistor

This paper presents the results of hot carrier stress experiments of a high voltage 0.35 μm n-channel lateral DMOS transistor. The stress induced degradation was investigated at different ambient temperatures over a wide range of both gate- and drain-stress voltages. In order to explain the observed device degradation under these stress conditions, the combined influence of hole- and electron induced degradation have to be taken into account. A physical explanation of the observed effects is provided and a phenomenological degradation model is suggested.