Non destructive 3D chip inspection with nano scale potential by use of backside FIB and backscattered electron microscopy

Three dimensional chip inspection with sub micron resolution is essential for physical failure analysis. The established approaches often require cross sections, destroying the device under test. This paper presents a non destructive way to gain precise geometrical information of the transistor- and metal-one-layer with the use of state of the art backside FIB preparation and backscattered electron microscopy.