OBIRCH analysis of electrically stressed advanced graphic ICs

Failed customer ICs and purposely electrically stressed ICs were analyzed using OBIRCH. A total of four abnormal thermally sensitive sites were localized within the LDT clock divider circuit and the PLL ESD protection structure. Failed customer ICs and electrically stressed ICs presented OBIRCH sensitive areas in those sites in different combinations. OBIRCH analysis confirmed that high voltage CDM type stress was at the root cause of the customer IC failure, even though the electrical test results did not fully correlate. Physical analysis results confirmed the OBIRCH findings, and revealed source-to-drain melt silicon damage at both NMOS and PMOS transistors and punch-through holes at capacitor edges.