A case study of defects due to process marginalities in deep sub-micron technology

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in and below deep sub-micron technology node. Most of the defects causing chip leakage are detectable with only one of the failure analysis (FA) tools such as liquid crystal detection (LCD) or photon emission microscope (PEM). However, due to process marginalities some defects are often not detectable with only one FA tool [Hung-Sung Lin, Wen-Tung Chang, Chun-Lin Chen, Tsui-Hua Huang, Vivian Chiang, Chun-Ming Chen. A study of asymmetrical behaviour in advanced nano SRAM devices. In: 13th IPFA proceedings; July 2006. p. 63–6; Kruseman Bram, Majhi Ananta, Hora Camelia, Eichenberger Stefan, Meirlevede Johan. Systematic defects in deep sub-micron technologies. ITC international test conference, 2004. p. 290–9.]. This paper present an example of an abnormal power consumption process related defect which could only be detected with more advanced FA tools.