The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs

The thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of 〈100〉/(100) 90 nm SOI nMOSFETs were studied in detail. Additionally, we also inspected the low frequency characteristic with low-frequency noise investigation for FB-SOI nMOSFETs. Experimental results show that devices with 1100 Å HS CESL possess worse characteristics and hot-carrier-induced degradations than devices with 700 Å HS CESL due to serious stress-induced defects happen. The lower plateau of Lorentzian noise spectrum observed from input-referred voltage noise (Svg) implies higher leakage current for the devices with 1100 Å HS CESL. On the other hand, we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD.