Hardening silicon-on-insulator nMOSFETs by multiple-step Si+ implantation

• Multiple-step Si implantation is used to harden buried oxides in SOI wafers.
• Single implant dose is determined by XRD technique.
• Pseudo-MOS characterization is applied to examine film quality.
• Hardened partially-depleted SOI devices show tolerance up to 1.0 Mrad(Si).

A novel technique is proposed to improve total irradiation dose (TID) hardness of buried oxides in a 0.13 μm silicon-on-insulator (SOI) technology. Multiple-step Si ion implantation is implemented to avoid silicon film amorphization. Each implant step introduces silicon ion implantation of a lower dose into buried oxides which creates an amorphous/crystalline (a/c) interface inside the silicon layer. Rapid thermal annealing (RTA) removes implant-induced lattice damages by silicon recrystallization reflected in a/c interface moving towards the top silicon surface. The thermal process prevents top silicon layers from total amorphization arising in the technique of single high dose implantation method. X-ray Diffraction (XRD) spectrum confirms the existence of the a/c interface and determines the single implant dose. Experimental results on pseudo-MOS and H-gate partially-depleted SOI n-type MOSFETs show radiation tolerance up to 1.0 Mrad(Si) though introduced metastable electron traps lead to I–V hysteresis and bias instabilities.