Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

• a parasitic SCR can be triggered even if off-chip decoupling is present
• transient interaction of the parasitic SCR structure with the surrounding circuitry causes an internal current injection which subsequently latches the circuit
• a mixed-mode simulation setup is designed which includes the parasitic SCR needs and all passive components with their parasitic
• additional on-chip decoupling improves the transient-induced latchup robustness

Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.