Low latency radiation tolerant self-repair reconfigurable SRAM architecture

• A radiation tolerant SRAM architecture able to deal with single and multi-bit errors is proposed.
• No extra cycles for detection/correction of the error are required. The correction is performed during the read cycle.
• Operation at high frequencies is provided even in worst corner conditions. When fault-free, the induced latency is zero.
• An accelerator circuit is proposed for higher repair frequencies.
• The architecture is reconfigurable with two provided configurations (Fault Tolerance and Full Capacity).

In this paper we present a low latency reconfigurable radiation tolerant memory architecture for mission-critical applications based on the RTSR (Radiation Tolerant Self-Repair) cell. The proposed architecture offers detection and correction during the read cycle at high frequencies. Through reconfiguration circuitry, the memory can operate in two modes, one providing soft error tolerance and another geared towards increased (× 3) memory capacity. Compared to the conventional Triple Modular Redundancy, the proposed memory architecture provides radiation tolerance for single and multi-bit upsets with improved latency, area and power characteristics. An enhanced version of the RTSR-based memory architecture is also presented (RTSR+), whereby we can boost performance by embedding a small accelerator circuit. From simulation results on a layout implementation of the proposed memory architecture in a 65 nm technology, with PVT variations and parasitics taken into account, the RTSR+ architecture can achieve up to 200% performance increase compared to the RTSR architecture in certain memory configurations.