Microscopic scale characterization and modeling of transistor degradation under HC stress

This paper presents a theoretical framework about interface states creation rate from SiH bond breaking at the Si/SiO2 interface during Hot Carrier (HC) stress. It involves two mains mechanisms of bond breaking through incident carriers, either being very energetic or very numerous but less energetic. This concept allows physical modeling of the reliability of MOS transistors, for different HC stress conditions. Simulation is validated by measurement of both defect lateral profiles and degradation of MOS parameters. This poses a general framework for the study of HC degradation at defect level.