MOS power transistor model for Electromagnetic Susceptibility analysis

This paper deals with the susceptibility of MOS power transistors to radio frequency interference. An nMOS connected in the low-side configuration is considered and the failures that result from disturbances superimposed onto the drain-source nominal signal are discussed. The susceptibility of power transistors to electromagnetic interference is analyzed referring to small-signal equivalent circuits and the influence of the gate-source input loop impedance is highlighted. To these purpose a distributed gate resistance model is used in small-signal analysis and time domain simulations. The results obtained with this model are in a much better agreement with the experimental results than those obtained with commonly used lumped models are. On the basis of these investigations some technology and design solutions are proposed to reduce the susceptibility to electro-magnetic disturbances affecting the drain-source terminals of a power MOS transistor connected in the low-side configuration.