Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.