A review of the use of electro-thermal simulations for the analysis of heterostructure FETs

This paper deals with using device-level numerical simulations for the investigation of the electro-thermal behavior of a GaAs-based heterostructure FET. We show a way of dealing with the software/hardware limitations related with the huge disproportion between the electrically active region and the volume relevant to heat outflow. We study very wide simplified structures to obtain guidelines for building up a reduced grid and proper boundary conditions for the complete simulation of the electro-thermal behavior of the FET. As an application example, we use this approach to simulate the military standard (MIL-STD) method for the measurement of the thermal resistance of GaAs FETs, thus discussing its accuracy and limitations. We also show that in multi-finger structures a single channel temperature such as that obtained by electrical thermal resistance extraction techniques cannot satisfactorily describe the FET’s thermal behavior. Finally, we briefly dwell on a comparison between 2D and 3D simulations.