Heat stress exposing performance of deep-nano HK/MG nMOSFETs using DPN or PDA treatment

• The electrical performance of nMOSFETs as L = 0.1 and 0.03 μm with DPN treatment was measured.
• The electrical characteristics of nMOSFETs as L = 0.1 and 0.03 μm with PDA treatment were extracted.
• After heat stress, the degradation of I–V curves for nMOSFETs with both treatments was shown.
• The relationship between the sub-threshold swing and the Vt was illustrated.
• The degradation mechanisms for both treatments were exposed.

Decoupled plasma nitridation (DPN) or post-deposition annealing (PDA) process after high-k (HK) deposition to repair the bulk traps or the oxygen vacancy in gate dielectric is an impressive choice to raise up the device performance. Before heat stress, the electrical performance in drive current, channel mobility and subthreshold swing with both treatments was approximate, except the higher annealing atmosphere causing the thicker interfacial layer and reducing the overall related dielectric constant. After temperature stress, the electrical performance for all of the tested devices was slightly deteriorated. The degradation degree for electrical performance with PDA treatment group was the worst case due to NH3 atmosphere forming Si–H bond on the channel surface, which was broken after stress and produced more interface state reflected with the increase of subthreshold swing.

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