Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

• Warm spare gate is addressed in the revised paper.
• Cold spare and SEQ gates are revised to better modeling in stochastic logic.
• Temporal gates are presented and their equivalents in stochastic logic are explained.
• Hardware implementation due to need of speedup is discussed.
• The model presented in this paper covers other probability distributions like Weibull.

This paper presents accurate models for the analysis of fault trees based on stochastic logic. To produce the models, probabilistic analysis of static, dynamic and temporal gates is carried out and the probability models are converted to their equivalent stochastic logic gates. A hardware template is also designed for each stochastic logic gate. In the proposed method, users provide fault rates of basic events and immediately evaluate system reliability. Experimental results show that the proposed method is more accurate than previous methods using the proposed stochastic logic gates for dynamic and temporal fault trees. The formula was validated using the Markov model for exponential failure distribution events. The proposed model is applicable for both exponential and non-exponential distributions.