Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

• This paper explores stress induced mobility changes over three major bumping processes.
• Results can be used either to increase current or to decrease circuit variability.
• MOSFET placement rules are drawn for SnAg, copper pillar and μ copper pillar bumping.
• Stress states are qualitatively similar whereas effective mobility variations are distinct.
• nMOS are sensitive to their location and channel orientation drives pMOS behavior.

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.It is demonstrated that stress effects on mobility are widely dependent on the integration flow, and transistor placements must be considered accordingly. Despite the fact that, qualitatively speaking, the generated stress states are quite similar for whole bumping schemes, the quantitative variations of each stress components in combination with the piezo resistive coefficients of silicon lead to distinct effective mobility variations. As a consequence, design rules and keep out zones can be optimized specifically for each assembly technology. More precisely, it is advised to avoid nMOS placement directly below the bump in flip chip devices, for which the mobility can be degraded by almost 5%. In these cases keep out zones must be considered. Reversely, in the case of 3DICs, the performances of nMOS are improved by more than 2% in that region, which means that no restriction is required and silicon area can hence be saved. As for the p type carriers, variability is sensitive to channel orientation rather than their location with respect to the bump: more precisely, the transport direction must be azimuthally oriented, and radially oriented pMOS are proscribed. Maximum variations of about ±5% are found for the copper pillar flip chip configuration. Thanks to a comprehensive analysis, FEoL designers will be able to integrate BEoL and packaging constraints during the conception phases of advanced semiconductor products.