Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis

A framework is proposed to analyze the impact of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory, embedded within a system running a variety of standard benchmarks. We study DC noise margins in conventional 6T SRAM cells as a function of NBTI/PBTI degradation and provide insights on memory reliability under realistic use conditions.