A low-cost built-in error correction circuit design for STT-MRAM reliability improvement

• We analyse and model the reliability issue in STT-MRAM.
• We present a low-cost OLSC circuit to improve STT-MRAM reliability.
• Built-in-form implementation using STT-MRAM-based logic acts as an inner code.
• Its simple codec provides very low area and high speed.
• Modular codec structure enables adaptive error correction capability.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) possesses various merits, such as non-volatility, low power and high speed. It has been considered as a promising non-volatile memory candidate used universally in logic computing, cache and storage applications. However it suffers from serious reliability issues compared with conventional schemes, especially in deep submicron technologies. This paper proposes a low-cost built-in error correction circuit to improve STT-MRAM reliability. Its straightforward “XOR” encoder and one-step majority-voting decoder provide much lower area and higher speed compared with conventional ECCs, and its modular codec structure allows adaptive error correction capability according to the system requirement. Simulation based on a compact STT model and STMicroelectronics 40 nm technology node was carried out to confirm its effectiveness.