Influence of the interface trap location on the performance and variability of ultra-scaled MOSFETs

• We examine the influence of interface trap location on the device performance.
• Device simulations are used to study the impact of a single interface trap.
• Device variability due to randomness in the trap location was investigated.
• Trap located close to the drain edge of the channel showed most degradation.
• Influence of drain biases on the threshold shift was also looked at.

The study reported herein examines the influence of the location of the interface traps along the channel in an nMOSFET on the device performance. Device simulations were performed to understand the effect of a single interface trap on the device band structure and electrical characteristics. The dependence of the biasing conditions on the study was also considered. Variability in the device performance due to the randomness in the trap location was also investigated. The study was helpful in identifying the critical device location where traps are more effective.