On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

• System Level ESD.
• On-chip measurements.
• IC design.

Electro Static Discharge (ESD) is one of the major causes of electronic system failures. Reliability of ICs within the applications is strongly related to the on-chip propagated waveform of the ESD stress on the power supplies, the substrate and through the protections. This paper presents an on-chip oscilloscope developed for in-situ measurement of real ESD event in 65 nm CMOS technology. Dynamic measurements of overshoots, substrate fluctuation and onchip radiated fields presented in this paper are performed with 20 GHz bandwidth.