Impact of back gate biases on hot carrier effects in multiple gate junctionless transistors

The impacts of back gate biases on hot carrier induced device degradation in multiple gate junctionless (JL) transistors have been investigated experimentally. The drain current was decreased after hot carrier stress without a polarity of back gate stress bias. The impacts of back gate bias on the drain current degradation are more significant in JL transistors than inversion mode (IM) transistors. When a positive back gate bias is applied, the interface coupling effect is more sensitive in JL transistors because the inversion channel is located at the centroid of the Si film in JL transistors but the back channel is located at the back interface in IM transistors. 3-dimensional device simulation was performed using ATLAS software to investigate the impact of negative VBS on hot carrier degradation in JL transistors.