The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design

In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective drive current in strain engineered devices. Width dependent change in drive strength causes WP/WN ratio (also referred to as ‘β’) in inverters to change with inverter scaling factor ‘S’. If not accounted for, this results into a suboptimal circuit design and unaccounted change in performance. Finally, considering the narrow width effects (NWEs), we propose a model to design variable-taper CMOS buffer. In our model the taper factor from one inverter stage to the next is a variable and depends upon the location of an inverter in the buffer chain. We observe that buffer designed using our model takes less area, consumes less power and gives marginal improvement in delay also.