Unit capacitor array based SAR ADC

This paper proposes a new successive approximation register analog-to-digital converter by using a unit capacitor array to implement the digital-to-analog converter. Under the same differential non-linearity specification, the proposed method can consume orders of magnitude less switching power and chip area than all existing solutions, including those using a binary weighted capacitor array (with or without a bridge capacitor) and those using a split capacitor array. The claimed benefits of the proposed method are verified by behavioral simulations.