Studies of the quality of GdSiO–Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C–V, I–V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C–V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.