Reliability of thin ZrO2 gate dielectric layers

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO2 gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (Vt) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.