کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
549362 | 872362 | 2011 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Back-end soft and hard defect monitoring using a single test chip
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed using a ST-Microelectronics’ 130 nm technology, is given. This structure is based on a SRAM memory array for detecting hard defects. Moreover each memory cell can be configured in the Ring Oscillator (RO) mode for back-end PV characterization. The structure is tested in both modes (SRAM, RO) using a single test flow. The test data analysis method is presented and applied to experimental results to confirm the ability of the structure to monitor PV and defect density.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 51, Issue 6, June 2011, Pages 1136–1141
Journal: Microelectronics Reliability - Volume 51, Issue 6, June 2011, Pages 1136–1141
نویسندگان
Fabrice Rigaud, Jean-Michel Portal, Hassen Aziza, Didier Nee, Julien Vast, Fabrice Argoud, Bertrand Borot,