Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material

A vital parameter interconnect capacitance in the ULSI has been investigated in this paper. The potential and static capacitance under the metal line strip has been determined by solving the Poisson’s equation by finite difference method. It has been observed that, the lowering of interconnect width and spacing between the two metal lines affect significantly on coupling capacitance. The total capacitance (CT) is dominantly being contributed by coupling capacitance (Cc). The calculations of CT have been made by using the low dielectric constant (k = 2.97) of the deposited hybrid thin film.