Switch-level emulation of strength-base soft error detection

Modern nanometer circuits have become more prone to soft errors necessitating faster and more reliable error detection techniques. Simulation-based soft error detection has been popular but is limited by its inability to handle complex circuits and high run-time. FPGA-based soft error detection methods can be effectively used to overcome the speed limitation of simulation as well as handle circuits with much higher complexity. The paper presents a novel strength-based soft error emulation method targeting soft errors caused by transient pulses of magnitude less than logic threshold. The impact of transient injection location on soft error coverage is analyzed and the idea of using drain of a transistor as transient injection location is presented. Furthermore, the concept of transient equivalence is applied to minimize resource overhead as well as speed-up soft error detection process. Advanced switch-level models are designed using gate-level structure and used to implement switch-level equivalents of ISCAS’85 benchmarks. The experimental results reported for ISCAS’85 benchmarks show that an average soft error coverage of 0.7–0.8 was achieved using the proposed strength-based detection with drain as transient injection location. The application of transient equivalence resulted in speed-up of emulation by 2.875 and reduced the memory utilization by 65%. The emulation-based soft error detection achieved significant speed-up of the order of 106 as compared to a customized simulation-based method.