Assembly reliability assessment and life estimation for a stacked area array device

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next-generation of monolithic memory devices. Stacking components helps in the transition to higher-density memory while the design and production capability for the next-generation of memory devices is being developed. However, on the other hand, the complex nature of stacked Chip Scale Package (CSP) components mandates a thorough review of the assembly processes and a detailed reliability assessment for these packages.The research objective was to study the assembly reliability of stacked CSP components assembled on a densely populated lead-free memory module utilizing mirror imaged component placements. The assessment was carried out using thermal cycling and mechanical shock tests. The data collected from thermal cycling was also used for failure modeling and life estimation. The methodology for estimating field life was established and the field life was estimated for a server application. The results proved that stacked CSP components can be reliably assembled. The module using stacked CSP components surpassed the life expectancy for server applications, which is 10 years.