Simulation and modelling of VDMOSFET self protection under TLP-stress

We present a simple and practical model for modelling the electrical behaviour of scalable vertical diffused MOSFETs (VDMOSFETs) under TLP stress. The trigger current is found to be dependent from gate–source voltage and geometry. A scalable model for analog circuit simulation is developed.As application example, self protection of VDMOS in resistive coupled gate configuration is investigated. For this purpose the device behaviour under TLP stress is modelled. The model is shown to predict VDMOS self protection under TLP stress for a wide range of geometries in an excellent way. A comprehensive analytical model calculation is added which explains the range of model validity. Within this range maximum HBM rating of the resistive gate coupled devices is predicted correctly.